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 Session Numbers
1 UVM Applications - I
1T Preparing for IEEE UVM Plus UVM Tips and Tricks
2 Design and Modeling Approaches
2T SVA Advanced Topics: SVAUnit and Assertions for Formal
3 Low-Power Verification
3T Cut Your Design Time in Half with Higher Abstraction
4P Poster Session
4T SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling
5 SystemVerilog Programming and Techniques
5T Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips
6 Advanced Fault Analysis Techniques
6T Developing Innovative Verification and Debug Methodologies Using Synopsys VC Apps
7 Effective Emulation
7T Methodology for Addressing Mixed-Signal SoC Verification Challenges
8 UVM Applications - II
8T Using Portable Stimulus for SoC Verification as Applied on Mobile, Networking and Server Designs
9 Advanced Mixed-Signal Practices
9T Back to Basics: Doing Formal the Right Way
10 Verification Processes and Resource Management
10T Validate Your Next Generation SoC Memories Utilizing Advanced Verification Techniques
11 UVM Applications - III
11T It All Starts with Quality Design
12 Formal Techniques
12T Solving the Next Big SoC Challenges with FPGA Prototyping and Stratix 10
13 SystemVerilog and Other Languages