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 Session Numbers
1 TLM and IPXACT
1L Lightning Session 1
1T Advanced UVM Coding Techniques
2 AMS and Power
2L Lightning Session 2
2T ISO26262 - This Changes Everything
3 Verification Flow and Tools
3T How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges
4 UVM in Practice
4T Formal Verification - Too Good To Miss
5 UVM Deep Dive
5T Advanced UVM tips & tricks - tutorial
6 Advanced Verification
6T UVVM - A Game Changer for FPGA VHDL Verification
7 Gate Level Simulation and Mixed-Signal Verification
7T Platform Level Design : IP-XACT and SoC Verification
8 Mixed-Signal Verification
8T Simplified Assertion Abstraction to Code High-reliability Requirements for the Formal Verification of Safety Critical and Other Designs
9 Design Challenges
9T An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to Software Driven Chip Level Verification Across Simulation and Emulation
10 Functional Safety
10T Model Driven Approach to Software Driven Verification
11 SystemC Evolution I
11T Shadow Simulation : A New Verification Methodology for Configurable Logic
12 SystemC Evolution II
12T Back to Basics: Doing Formal the Right Way
13 Rethinking HDLs
13T UVM-SystemC goes random - Introducing CRAVE in UVM-SystemC
14T Applying UPF 3.0 for Early, System-level Power Analysis of SoCs with DDR Memories
15T Advancing the SystemC Ecosystem
16T Designing Safe Cars - How to Ensure Your Semiconductor Design Meets ISO-26262 Fault-Safety Requirements
20 The Road Ahead for the Securely Connected, Self-Driving Car
21 Design and Verification Focus in ARM TSG
22 Gala Dinner Presentation - Moore's Law and the Transition from Chip-Centric Design to System-Level Design
35 Closing Session - Best Paper Awards
36 Exhibit Floor Open
38 Exhibit Floor Open
50 Security in the Automotive Value Chain
51 Accellera Special Townhall Meeting