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 Session Numbers
1 UVM-1
1P Panel: Imagining How Artificial Intelligence Could Reshape the Verification Landscape
1T Tutorial 1: Building Smart SoCs - Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators
2 SystemC
2P Panel: Applying the New Breed of Automotive Specific, Next-Generation Verification Technologies
2T Tutorial 2: RISC-V Compliance and Verification Techniques for Processor Cores Including Optional Custom Extensions
3 Generating Stimulus
3T Tutorial 3: Advance your Design and Verification Flow Using IP-XACT
4 Advanced Verification 1
4T Tutorial 4: Applying Design Patterns to Maximise Verification Reuse @Block, Subsystem and System-on-Chip Level
5T Tutorial 5: Early Performance Verification of Embedded Inferencing Systems Using Open-Source SystemC NVIDIA MatchLib
6 RISC-V and Advanced ISS
6T Tutorial 6: 5G New Radio Explained: From 3GPP 5G Standard Fundamentals To 5G-Enabled Verticals
7 Formal Verification
7T Tutorial 7: UVM-SystemC – Functional Coverage & Constrained Randomization
8 SOC Verification
8T Tutorial 8: QED & Symbolic QED: Pre-Silicon Verification, Post-Silicon Validation, Industrial Results
9 UVM-2
9T Tutorial 9: Next Gen System Design and Verification for Transportation
10 Emulation
10T Tutorial 10: RISC-V Integrity: A Guide for Developers and Integrators
11 System Level Design
11T Tutorial 11: Unified Functional Safety Verification Platform for ISO 26262-Compliant Automotive Designs
12 Advanced Verification 2
12T Tutorial 12: Cadence® vManager TM Platform and Virtuoso® ADE Verifier : Leading Edge Technologies Provide the Methodology for Mixed-Signal Verification Closure
13T Tutorial 13: Solve Software Coding Challenges with Exciting New Drone Technology
14T Tutorial 14: Safety and Security Aware Pre-Silicon Hardware/Software Co-Development
15T Tutorial 15: Revitalizing Automotive Safety Hard and Soft Error Approaches
16T Tutorial 16: Be a Sequence Pro to Avoid Bad Con Sequences