Archive

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TUESDAY February 28, 2012, 9:00 AM - 10:30 AM


ARCHIVED SESSION 1
Low-Power Techniques
Moderator: Charles Dawson - Cadence Design Systems, Inc.


1.1Low-Power SoC Verification: IP Reuse and Hierarchical Composition Using UPF
 
 Speaker: Amit Srivastava - Mentor Graphics Corp.
 Authors: Amit Srivastava - Mentor Graphics Corp.
Rudra Mukherjee - Mentor Graphics Corp.
Erich Marschner - Mentor Graphics Corp.
Chuck Seeley - Mentor Graphics Corp.
Sorin Dobre - Qualcomm, Inc.
1.2The Case for Low-Power Simulation-to-Implementation Equivalence Checking
 
 Speaker: Himanshu Bhatt - Cadence Design Systems, Inc.
 Authors: Himanshu Bhatt - Cadence Design Systems, Inc.
John Decker - Cadence Design Systems, Inc.
Hiral Desai - Cadence Design Systems, Inc.
1.3Is Power State Table (PST) Golden?
 
 Speaker: Ankush Bagotra - Synopsys, Inc.
 Authors: Ankush Bagotra - Synopsys, Inc.
Neha Bajaj - Synopsys, Inc.
Harsha Vardhan Dasagrandhi - Synopsys, Inc.