Archive

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TUESDAY February 28, 2012, 11:00 AM - 12:30 PM


ARCHIVED SESSION 4
Verification Benchmarking and Efficiency
Moderator: Clifford Cummings - Sunburst Design, Inc.


4.1Yikes! Why is My SystemVerilog Testbench so Slow?
 
 Speaker: Justin Sprague - Cadence Design Systems, Inc.
 Authors: Frank Kampf - IBM Corp.
Justin Sprague - Cadence Design Systems, Inc.
Adam Sherer - Cadence Design Systems, Inc.
4.2How I Learned to Stop Worrying and Love Benchmarking Functional Verification!
 
 Speaker: Michael G. Bartley - Test and Verification Solutions
 Authors: Michael G. Bartley - Test and Verification Solutions
Mike Benjamin - Test and Verification Solutions
4.3Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient
 
 Speaker: Stuart Sutherland - Sutherland HDL, Inc.
 Authors: Stuart Sutherland - Sutherland HDL, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.