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WEDNESDAY February 29, 2012, 8:00 AM - 10:00 AM

ARCHIVED SESSION 8
Getting to Coverage Closure

Moderator:
Gordon McGregor - Verilab, Inc.




8.1Relieving the Parameterized Coverage Headache
 
 Speaker: Christine Lovett - Xilinx, Inc.
 Authors: Christine Lovett - Xilinx, Inc.
Bryan Ramirez - Xilinx, Inc.
Stacey Secatch - Xilinx, Inc.
Michael Horn - Mentor Graphics Corp.
8.2Bringing Continuous Domain into SystemVerilog Covergroups
 
 Speaker: Prabal K. Bhattacharya - Cadence Design Systems, Inc.
 Authors: Prabal K. Bhattacharya - Cadence Design Systems, Inc.
Donald J. O'Riordan - Cadence Design Systems, Inc.
Swapnajit Chakraborti - Cadence Design Systems, Inc.
Scott Little - Intel Corp.
Vaibhav Bhutani - Cadence Design Systems, Inc.
8.3Systematically Achieving CDC Verification Closure Based on Coverage Models and Coverage Metrics
 
 Speaker: Ashish Hari - Mentor Graphics Corp.
 Authors: Ashish Hari - Mentor Graphics Corp.
Yogesh Badaya - Mentor Graphics Corp.
8.4Graph-IC Verification
 
 Speakers: Dennis Ramaekers - ST-Ericsson
Gregory Faux - STMicroelectronics
 Authors: Dennis Ramaekers - ST-Ericsson
Gregory Faux - STMicroelectronics

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